Laser repair operation

ABSTRACT

A method of conducting a laser repair operation. A silicon wafer has a plurality of chips thereon. Each chips has a plurality of bonding pads, a plurality of testing pads, a plurality of fuses and a passivation layer for protecting the chips. The passivation layer exposes the bonding pads and the testing pads. A bump-forming process is conducted to form a bottom metallic layer and a bump sequentially over each bonding pad. Only a bottom metallic layer is formed over each testing pad. The bumps are formed, for example, by electroplating or printing. Testing is carried out by probing various bottom metallic layers above the testing pads. Finally, a laser repair is conducted.

BACKGROUND OF THE INVENTION

[0001] 1. Field of Invention

[0002] The present invention relates to a type of laser repair. Moreparticularly, the present invention relates to a laser repair operationof a silicon wafer before conducting a bump-forming process.

[0003] 2. Description of Related Art

[0004] Integrated circuits are complicated electronic products whosemanufacturing involves a series of major activities including integratedcircuit design, wafer fabrication, wafer testing and wafer packaging. Ingeneral, manufactured integrated circuits must undergo a series of testbefore shipping just to ensure a high product quality. The resultsprovided by these tests are essential also for repairing anymalfunctional integrated circuits. As usual, natural yield of integratedcircuit is relatively low. Hence, on discovering some defects in thecircuit of a silicon chip, a laser repair operation is often conducted.In the repair process, a number of fuses is generally burnt by a laserso that specially designed redundant bit lines can replace the defectivebit lines. Ultimately, product yield of the wafer may increaseconsiderably.

[0005]FIGS. 1 through 4 are schematic cross-sectional views showing theprogression of steps in a conventional laser repair operation. First, asilicon wafer is provided. The wafer has a plurality of silicon chips100. In FIG. 1, only a single silicon chip 100 is shown. The siliconchip 100 includes a plurality of bonding pads 102, a plurality oftesting pads 104, a plurality of fuses 106 and a passivation layer 108.The passivation layer 108 protects the silicon chip 100 and includesopenings that expose the bonding pads 102 and the testing pads 104.

[0006] As shown in FIG. 2, a probe 110 is used to carry out a testingoperation. A probe mark 112 is formed on the testing pad 104. When anydefects are found the circuit, a laser repair operation is next carriedout. In a laser repair, a laser beam aims at a fuse 106, burning aportion of the passivation layer 108 and melting open the protectivefuse 106 to form a fused section 114. Specially designed redundant bitlines then replace the defective bit lines. Through the laser repairoperation, the yield of silicon chips on a wafer is greatly boosted.

[0007] As shown in FIG. 3, a bump-forming process is carried out afterthe laser repair operation. The bump-forming process mainly includesunder ball metallurgical (UBM) layer fabrication and bump production.Since the fabrication of UBM layer often requires etching to formpattern, a second passivation layer 116 is formed over the silicon chip100 to prevent unwanted etching of the testing pad 104 and the burntsection 114. To be useful as a protective layer, the second passivationlayer 116 needs also to undergo a photolithographic and etching processto form an opening 117 that exposes the bonding pads 102.

[0008] As shown in FIG. 4, a conductive layer is formed over the chip100. Photolithographic and etching processes are conducted to form abottom metallic layer 118 over the bonding pad 102. Finally, a bump 120is formed over the bottom metallic layer 118, thereby completing theprocess of conducting a laser repair and fabricating bumps on a wafer.

[0009] Because a bump-forming process is carried out after a laserrepair and an etching step is used to form the bottom metallic layer inthe bump-forming process, a second passivation layer is required toprotect the laser burnt fuse area. In addition, a masking step isrequired to form an opening that exposes the bonding pad in the secondpassivation layer so that a bump can be formed on the bonding pad. Ingeneral, the coating of a second passivation layer and the forming of anopening in the second passivation layer complicate the fabricationprocess and increase production cost.

SUMMARY OF THE INVENTION

[0010] Accordingly, one object of the present invention is to provide alaser repair operation. The laser repair operation includes fabricatinga bottom metallic layer on bonding pads and testing pads, conducting atesting operation by probing the bottom metallic layer on the testingpads, and finally performing a laser repair. Since etching that mightdamage the exposed fuse is no longer conducted after a laser repair,forming a second passivation for protecting the broken fuses isunnecessary.

[0011] To achieve these and other advantages and in accordance with thepurpose of the invention, as embodied and broadly described herein, theinvention provides a method of conducting a laser repair operation. Asilicon wafer having a plurality of chips thereon is provided. Eachchips has a plurality of bonding pads, a plurality of testing pads, aplurality of fuses and a passivation layer for protecting the chips. Thepassivation layer exposes the bonding pads and the testing pads. Abump-forming process is conducted to form a bottom metallic layer and abump sequentially over each bonding pad. A bottom metallic layer isformed over each testing pad. The bumps are formed, for example, byelectroplating or printing. Thereafter, testing is carried out byprobing various bottom metallic layers above the testing pads. Finally,a laser repair is conducted.

[0012] It is to be understood that both the foregoing generaldescription and the following detailed description are exemplary, andare intended to provide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The accompanying drawings are included to provide a furtherunderstanding of the invention, and are incorporated in and constitute apart of this specification. The drawings illustrate embodiments of theinvention and, together with the description, serve to explain theprinciples of the invention. In the drawings,

[0014]FIGS. 1 through 4 are schematic cross-sectional views showing theprogression of steps in a conventional laser repair operation;

[0015]FIGS. 5 through 9 are schematic cross-sectional views showing theprogression of steps in a laser repair operation according to a firstpreferred embodiment of this invention; and

[0016]FIGS. 10 through 14 are schematic cross-sectional views showingthe progression of steps in a laser repair operation according to asecond preferred embodiment of this invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] Reference will now be made in detail to the present preferredembodiments of the invention, examples of which are illustrated in theaccompanying drawings. Wherever possible, the same reference numbers areused in the drawings and the description to refer to the same or likeparts.

[0018]FIGS. 5 through 9 are schematic cross-sectional views showing theprogression of steps in a laser repair operation according to a firstpreferred embodiment of this invention. As shown in FIG. 5, a siliconwafer having a plurality of chips 200 thereon is provided. Only a singlechip 200 is used in the following illustrations. The chip 200 includes,for examples, a plurality of bonding pads 202, a plurality of testingpads 204, a plurality of fuses 206 and a passivation layer 208. Thepassivation layer 208 has a plurality of openings that expose thebonding pads 202 and the testing pads 204.

[0019] As shown in FIG. 6, a conductive layer 217 is formed over thechip 200. The conductive layer 217, for example, can be atitanium/copper alloy layer or an aluminum/nickel/vanadium/coppercomposite layer formed by sputtering. A patterned photoresist layer 216is formed over the chip 200. The patterned photoresist layer 216 has aplurality of openings 215 that expose various bonding pads 202. Theseopenings 215 are subsequently used to pattern the locations for formingbumps. After patterning the photoresist layer 216, an electroplatingmethod may be used to deposit soldering material 222 into the openings215. The soldering material 222 includes, for example, a lead/tin alloy.

[0020] As shown in FIG. 7, the patterned photoresist layer 216 isremoved. A reflow operation is conducted so that the soldering material222 above the bonding pad 202 softens and turns into a bump 220 having aspherical shape due to surface tension.

[0021] As shown in FIG. 8, a portion of the conductive layer 217 isremoved so that only the conductive layer 217 underneath the bump 220and the conductive layer 217 above the testing pad 204 are retained.Hence, a bottom metallic layer 218 a is formed under the bump 220 and abottom metallic layer 218 b is formed over the testing pad 204. Sincethe bottom metallic layer 218 b covers the testing pad 204, a subsequenttest is conducted by probing the upper surface of the bottom metalliclayer 218 b. The results of the testing are identical to probing thetest pad 204 directly. In other words, the presence of the bottommetallic layer 218 b has no observable effect on the testing operation.

[0022] As shown in FIG. 9, a testing tool such a probing pin 210contacts the bottom metallic layer 218 b above the testing pad 204 andforms a test mark 212 on the bottom metallic layer 218 b. When defectsare found in the circuit, a laser repair is conducted by vaporizing thepassivation layer 208 above the fuse 206 and melting the fuse 206 toform a broken section 214. Hence, a redundant bit line now replaces theoriginal bit line. After the laser repair, overall yield of the chips200 in the silicon wafer is increased.

[0023] In the first embodiment, a second passivation layer with openingstherein for protecting the chip is not required. Hence, the laser repairoperation requires fewer steps and cost less.

[0024]FIGS. 10 through 14 are schematic cross-sectional views showingthe progression of steps in a laser repair operation according to asecond preferred embodiment of this invention. As shown in FIG. 10, asilicon wafer having a plurality of chips 300 thereon is provided. Onlya single chip 300 is used in the following illustration. The chip 300includes, for examples, a plurality of bonding pads 302, a plurality oftesting pads 304, a plurality of fuses 306 and a passivation layer 308.The passivation layer 308 has a plurality of openings that expose thebonding pads 302 and the testing pads 304.

[0025] As shown in FIG. 11, a conductive layer 317 is formed over thechip 300. The conductive layer 317, for example, can be atitanium/copper alloy layer or an aluminum/nickel/vanadium/coppercomposite layer formed by sputtering. A patterned photoresist layer 316is formed over the chip 300. The patterned photoresist layer 316 coversvarious bonding pads 302 and various testing pads 304 marking out thelocations for forming bottom metallic layers.

[0026] As shown in FIG. 12, using the patterned photoresist layer 316 asa mask, etching is conducted to remove a portion of the conductive layer317. Ultimately, a bottom metallic layer 318 a is formed over thebonding pads 302 and a bottom metallic layer 318 b is formed over thetesting pads 304. Thereafter, a solder printing step is conducted. Insolder printing, a stencil is provided or a patterned photoresist layer324 is formed over the chip 300. The stencil or the photoresist layer324 has a plurality of openings 315 that corresponds to the bonding pads302. After patterning out the bump locations, solder material 322 isapplied via a blade or other tools to fill the openings 315 of thestencil or the patterned photoresist layer 324.

[0027] As shown in FIG. 13, the stencil or the patterned photoresistlayer 324 is removed. A reflow operation is conducted to melt the soldermaterial 322 above the bonding pad 302 and form a bump 320 having aspherical profile due to surface tension. Since the bottom metalliclayer 318 b covers the testing pad 304, a subsequent test is conductedby probing the upper surface of the bottom metallic layer 318 b. Theresults of the testing are identical to probing the test pad 304directly. In other words, the presence of the bottom metallic layer 318b has no observable effect on the testing operation.

[0028] As shown in FIG. 14, a testing tool such a probing pin 310contacts the bottom metallic layer 318 b above the testing pad 304 andforms a test mark 312 on the bottom metallic layer 318 b. When defectsare found in the circuit, a laser repair is conducted by vaporizing thepassivation layer 308 above the fuse 306 and melting the fuse 306 toform a broken section 314. Hence, a redundant bit line now replaces theoriginal bit line. After the laser repair, overall yield of the chips300 in the silicon wafer is increased.

[0029] In the second embodiment, a second passivation layer withopenings therein for protecting the chip is not required. Hence, thelaser repair operation requires fewer steps and cost less than aconventional laser repair operation.

[0030] In conclusion, major advantages of the laser repair operation inthis invention include:

[0031] 1. Production of the bottom metallic layer is carried out beforelaser repair. Hence, broken fuses arc not exposed to any etchant. Sincethere is no exposure to damaging etchant, forming a benzene/cyclobutenelayer or polyimide layer (a second passivation layer) is unnecessary.

[0032] 2. Fewer production steps are required because a secondpassivation layer need not be formed over the chips. Furthermore,without the second passivation layer, steps for forming openings in thesecond passivation layer are unnecessary.

[0033] 3. The application of a probe to the bottom metallic layer abovethe testing pad produces results that are identical to the applicationof a probe to the testing pad directly. Moreover, the laser repairoperation can be carried out together with any bump-forming process.

[0034] It will be apparent to those skilled in the art that variousmodifications and variations can be made to the structure of the presentinvention without departing from the scope or spirit of the invention.In view of the foregoing, it is intended that the present inventioncover modifications and variations of this invention provided they fallwithin the scope of the following claims and their equivalents.

What is claimed is:
 1. A laser repair operation, comprising: providing asilicon wafer having a plurality of chips therein, wherein each chip hasa plurality of bonding pads, a plurality of testing pads, a plurality offuses and a passivation layer over the chip with the passivation layerhaving a plurality of openings exposing the bonding pads and the testingpads; conducting a bump-forming process such that a first bottommetallic layer and a bump are sequentially formed over each bonding padand a second bottom metallic layer is formed over each testing pad;performing a testing operation by probing the second bottom metalliclayer; and conducting a laser repair.
 2. The laser repair operation ofclaim 1, wherein the bump-forming process further includes: forming ametallic layer over the wafer; forming a pattern of the bump locations;coating a layer of solder material over the bump locations byelectroplating; conducting a solder reflow operation to form bumps; andremoving a portion of the metallic layer to form the first bottommetallic layer and the second bottom metallic layer.
 3. The laser repairoperation of claim 1, wherein the bump-forming process further includes:forming a metallic layer over the wafer; patterning the locations of thefirst bottom metallic layer and the second bottom metallic layer andremoving a portion of the metallic layer outside the patterned region toform the first bottom metallic layer and the second bottom metalliclayer; forming a pattern of the bump locations and printing soldermaterial onto the bump locations; and conducting a reflow operation toform the bumps.
 4. The laser repair operation of claim 2, wherein themetallic layer includes a titanium/copper alloyed composite layer. 5.The laser repair operation of claim 3, wherein the metallic layerincludes a titanium/copper alloyed composite layer.
 6. The laser repairoperation of claim 2, wherein the metallic layer includes analuminum/nickel/vanadium/copper alloyed composite layer.
 7. The laserrepair operation of claim 3, wherein the metallic layer includes analuminum/nickel/vanadium/copper alloyed composite layer.
 8. The laserrepair operation of claim 1, wherein performing the laser repairincludes breaking a fuse by aiming a laser beam at the fuse.
 9. Thelaser repair operation of claim 1, wherein after the laser repair,further includes a testing operation to confirm reconstitution of thechip circuit.
 10. A laser repair operation, comprising: providing asilicon wafer having a plurality of chips therein, wherein each chip hasa plurality of bonding pads, a plurality of testing pads, a plurality offuses and a passivation layer over the chip with the passivation layerhaving a plurality of openings exposing the bonding pads and the testingpads; forming a metallic layer over the wafer; patterning a plurality ofbump locations above the bonding pads and coating a layer of soldermaterial over the bump location by electroplating; conducting a reflowoperation to form the bumps; removing a portion of the metallic layer sothat a first bottom metallic layer is formed over each bonding pad and asecond bottom metallic layer is formed over each testing pad; performinga testing operation by probing a surface of the second bottom metalliclayer; and conducting a laser repair.
 11. The laser repair operation ofclaim 8, wherein the metallic layer includes a titanium/copper alloyedcomposite layer.
 12. The laser repair operation of claim 8, wherein themetallic layer includes an aluminum/nickel/vanadium/copper alloyedcomposite layer.
 13. The laser repair operation of claim 8, whereinperforming the laser repair includes breaking a fuse by aiming a laserbeam at the fuse.
 14. The laser repair operation of claim 8, whereinafter laser repair, further includes a testing operation to confirmreconstitution of the chip circuit.
 15. A laser repair operation,comprising: providing a silicon wafer having a plurality of chipstherein, wherein each chip has a plurality of bonding pads, a pluralityof testing pads, a plurality of fuses and a passivation layer over thechip with the passivation layer having a plurality of openings exposingthe bonding pads and the testing pads; forming a metallic layer over thewafer; removing a portion of the metallic layer so that a first bottommetallic layer is formed over each bonding pad and a second bottommetallic layer is formed over each testing pad; patterning a pluralityof bump locations above the bonding pads and coating a layer of soldermaterial over the bump location by printing; conducting a reflowoperation to form the bumps; performing a testing operation by probing asurface of the second bottom metallic layer; and conducting a laserrepair.
 16. The laser repair operation of claim 13, wherein the metalliclayer includes a titanium/copper alloyed composite layer.
 17. The laserrepair operation of claim 13, wherein the metallic layer includes analuminum/nickel/vanadium/copper alloyed composite layer.
 18. The laserrepair operation of claim 13, wherein performing the laser repairincludes breaking a fuse by aiming a laser beam at the fuse.
 19. Thelaser repair operation of claim 13, wherein after laser repair, furtherincludes a testing operation to confine reconstitution of the chipcircuit.